A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers

This paper presents a quadrature bandpass /spl Sigma//spl Delta/ modulator with continuous-time architecture. Due to the continuous-time architecture and the inherent anti-aliasing filter, the proposed /spl Sigma//spl Delta/ modulator needs no additional anti-aliasing filter in front of the modulato...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2002-12, Vol.37 (12), p.1628-1635
Main Authors: Henkel, F., Langmann, U., Hanke, A., Heinen, S., Wagner, E.
Format: Article
Language:English
Subjects:
Architecture
Band pass filters
Bandpass
Bandwidth
BiCMOS integrated circuits
Chips
Clocks
Delta-sigma modulation
Digital modulation
Dynamic range
Frequency
Modulators
Noise levels
Quadratures
Receivers
Voltage
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Summary:This paper presents a quadrature bandpass /spl Sigma//spl Delta/ modulator with continuous-time architecture. Due to the continuous-time architecture and the inherent anti-aliasing filter, the proposed /spl Sigma//spl Delta/ modulator needs no additional anti-aliasing filter in front of the modulator in contrast to quadrature bandpass /spl Sigma//spl Delta/ modulators with switched-capacitor architectures. The second-order /spl Sigma//spl Delta/ modulator digitizes complex analog I/Q input signals at 1-MHz intermediate frequency and operates within a clock frequency range of 25-100 MHz. The modulator chip achieves a peak signal-to-noise-distortion ratio (SNDR) of 56.7 dB and a dynamic range of 63.8 dB within a 1-MHz signal bandwidth and at a clock frequency of 100 MHz. Furthermore, it provides an image rejection of at least 40 dB. The 0.65-/spl mu/m BiCMOS chip consumes 21.8 mW at 2.7-V supply voltage.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2002.804332