Simple and accurate technique for extracting the parasitic resistances of the dual-gate GaAs MESFET

A procedure to extract the extrinsic resistances of the dual-gate GaAs MESFET (DGFET) is described. Six dc measurement setups are used to generate nine independent relations from which all the unknown extrinsic resistances of the DGFET are extracted. The described technique distinguishes between the...

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Bibliographic Details
Published in:IEEE microwave and wireless components letters 2002-08, Vol.12 (8), p.284-286
Main Authors: Ibrahim, M., Syrett, B., Bennett, J.
Format: Article
Language:English
Subjects:
Applied sciences
Bias
Channels
Circuit topology
DC generators
Devices
Electrical resistance measurement
Electronics
Equations
Equivalent circuits
Exact sciences and technology
FETs
Gallium arsenide
Gallium arsenides
Gates
MESFET circuits
MESFETs
Microwaves
Parameter extraction
Performance evaluation
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Transistors
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Description
Summary:A procedure to extract the extrinsic resistances of the dual-gate GaAs MESFET (DGFET) is described. Six dc measurement setups are used to generate nine independent relations from which all the unknown extrinsic resistances of the DGFET are extracted. The described technique distinguishes between the forward bias and the nonforward bias values of the channel resistance. The extrinsic resistances of 29 devices with different topologies are determined using the developed technique. The extracted resistances follow normal scaling rules versus gate width. The developed procedure is a practical and accurate approach to extract the extrinsic resistances of the DGFET.
ISSN:1531-1309
2771-957X
1558-1764
2771-9588
DOI:10.1109/LMWC.2002.801938