Design of a parameterizable silicon intellectual property core for QR-based RLS filtering

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2003-08, Vol.11 (4), p.659-678
• Main Authors: Lightbody, G., Woods, R., Walke, R.
• Format: Article
• Language: English
• Subjects: Applied sciences; Architecture; Arithmetic; Circuits; Design engineering; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Filtering; Filtering algorithms; Filtration; Hardware design languages; Information, signal and communications theory; Integrated circuits; Integrated circuits by function (including memories and processors); Intellectual property; Least mean square algorithms; Least squares methods; Resonance light scattering; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal and communications theory; Signal, noise; Silicon; Telecommunications and information theory; Time measurements; Timing; Very large scale integration
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2003.816142

The availability of an intellectual property core for recursive least squares (RLS) filtering could enable the RLS algorithm to replace the least mean squares algorithm in a wide range of applications. The goal of this study is to develop a parameterizable generic architecture for RLS filtering in the form of a hardware description language (HDL) description, which can be used to generate highly efficient silicon layout. The key issue is to develop a family of circuit architectures that are 100% efficient and locally connected. This paper presents a generic mapping for RLS filtering and circuit architectures that can be mapped to a range of application requirements. It outlines the transition from array to architecture covering detailed design issues such as timing and control generation. The result is a family of QR designs, which are parameterized in terms of architecture size, wordlength, performance, and arithmetic processor timing.