The split-gate flash memory with an extra select gate for automotive applications

• Published in: Solid-state electronics 2009-10, Vol.53 (10), p.1059-1062
• Main Authors: Tsair, Yong-Shiuan, Fang, Yean-Kuen, Wang, Yu-Hsiung, Chu, Wen-Ting, Hsieh, Chia-Ta, Lin, Yung-Tao, Wang, Chung S., Wong, Myron, Lee, Scott, Smolen, Richard, Liu, Bill
• Format: Article
• Language: English
• Subjects: Applied sciences; Channels; Design. Technologies. Operation analysis. Testing; Drains; Electronics; Exact sciences and technology; Extra select gate; Flash memory; Flash memory (computers); Gates; Integrated circuits; Integrated circuits by function (including memories and processors); Leakage current; Magnetic and optical mass memories; Microelectronic fabrication (materials and surfaces technology); Oxides; Program disturb; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Source-side injection; Split-gate; Storage and reproduction of information; Stresses; Voltage; Wordline oxide degradation
• ISSN: 0038-1101; 1879-2405
• DOI: 10.1016/j.sse.2009.06.015

In this paper, novel split-gate flash memory with an extra select gate (ESG) to improve the operation window has been investigated in details. Experimental results show that with the ESG (called 2.5T cell), the cell showed a better program wordline disturb window than that of the traditional split-gate flash memory cells (called 1.5T cell) around 0.5 V (at V s = 10 V). The offset of minimum drain voltage to avoid punch through disturb between without and with wordline stress for 2.5T cell and 1.5T cell are around 0.05 V and 0.2 V, respectively. We attribute these improvements in wordline disturb behaviors to the reduction of channel leakage current with the addition of ESG. During the erase stage, the gate oxide of the ESG suffers free stress, thus having better oxide integrity to resist the generation of channel leakage current. In addition, the ESG offers a reverse bias to retard the leakage current from drain to source.