A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM

• Published in: IEEE journal of solid-state circuits 2000-11, Vol.35 (11), p.1713-1721
• Main Authors: Takahashi, M., Nishikawa, T., Hamada, M., Takayanagi, T., Arakida, H., Machida, N., Yamamoto, H., Fujiyoshi, T., Ohashi, Y., Yamagishi, O., Samata, T., Asano, A., Terazawa, T., Ohmori, K., Watanabe, Y., Nakamura, H., Minami, S., Kuroda, T., Furuyama, T.
• Format: Article
• Language: English
• Subjects: Cameras; CMOS; CMOS technology; Code standards; Codec; Demultiplexing; Dynamic random access memory; Hardware; Large scale integration; Microprocessors; MPEG 4 Standard; Random access memory; Reduced instruction set computing; RISC processors; Speech codecs; Streaming media; Threshold voltage; Videophones
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.881219

A 240-mW single-chip MPEG-4 videophone LSI with a 16-Mb embedded DRAM is fabricated utilizing a 0.25-/spl mu/m CMOS triple-well quad-metal technology. The videophone LSI is applied to the 3GPP 3G-324M video-telephony standard for IMT-2000, and implements the MPEG-4 video SPL1 codec, the AMR speech codec, and the ITU-T H.223 Annex B multiplexing/demultiplexing at the same time. Three 16-bit multimedia-extended RISC processors, dedicated hardware accelerators, and a 16-Mb embedded DRAM are integrated on a 10.84 mm/spl times/10.84 mm die. It also integrates camera, display, audio, and network interfaces required for a mobile video-phone terminal. In addition to conventional low-power techniques, such as clock gating and parallel operation, some new low-power techniques are also employed. These include an embedded DRAM with optimized configuration, a low-power motion estimator, and the adoption of the variable-threshold voltage CMOS (VT-CMOS). The MPEG-4 videophone LSI consumes 240 mW at 60 MHz, which is only 22% of that for a conventional multichip design. Variable threshold voltage CMOS reduces standby leakage current to 26 /spl mu/A, which is only 17% of that for the conventional CMOS design.