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Block-based neural networks
This paper presents a novel block-based neural network (BBNN) model and the optimization of its structure and weights based on a genetic algorithm. The architecture of the BBNN consists of a 2D array of fundamental blocks with four variable input/output nodes and connection weights. Each block can h...
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Published in: | IEEE transaction on neural networks and learning systems 2001-03, Vol.12 (2), p.307-317 |
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container_title | IEEE transaction on neural networks and learning systems |
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creator | Moon, S W Kong, S G |
description | This paper presents a novel block-based neural network (BBNN) model and the optimization of its structure and weights based on a genetic algorithm. The architecture of the BBNN consists of a 2D array of fundamental blocks with four variable input/output nodes and connection weights. Each block can have one of four different internal configurations depending on the structure settings, The BBNN model includes some restrictions such as 2D array and integer weights in order to allow easier implementation with reconfigurable hardware such as field programmable logic arrays (FPGA). The structure and weights of the BBNN are encoded with bit strings which correspond to the configuration bits of FPGA. The configuration bits are optimized globally using a genetic algorithm with 2D encoding and modified genetic operators. Simulations show that the optimized BBNN can solve engineering problems such as pattern classification and mobile robot control. |
doi_str_mv | 10.1109/72.914525 |
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Simulations show that the optimized BBNN can solve engineering problems such as pattern classification and mobile robot control.</description><subject>Arrays</subject><subject>Blocking</subject><subject>Computer simulation</subject><subject>Encoding</subject><subject>Field programmable gate arrays</subject><subject>Genetic algorithms</subject><subject>Hardware</subject><subject>Logic</subject><subject>Mobile robots</subject><subject>Neural networks</subject><subject>Pattern classification</subject><subject>Programmable logic arrays</subject><subject>Reconfigurable logic</subject><subject>Robot control</subject><subject>Two dimensional</subject><issn>1045-9227</issn><issn>2162-237X</issn><issn>1941-0093</issn><issn>2162-2388</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2001</creationdate><recordtype>article</recordtype><recordid>eNqF0U1LAzEQBuAgiq3Vg1cFEQ-Kh62ZyfdRi19Q8KLnsJvNQttttyZdxH9vZBcFD_Y0gXkyMPMScgx0DEDNjcKxAS5Q7JAhGA4ZpYbtpjflIjOIakAOYpxTmhCV-2QAGjlnWgzJ6V3duEVW5NGX5yvfhrxOZfPRhEU8JHtVXkd_1NcReXu4f508ZdOXx-fJ7TRzHHGTKdSFkJUvCy8VCp0zAAEFcllxVpYlZbxiYJhiGmmljYQCdKXQgHMe0LERuermrkPz3vq4sctZdL6u85Vv2mjTbpJTAXSrVIxxwaQRSV7-K1GDNsKY7VBKxgzHBC_-wHnThlU6jDVItVSM6oSuO-RCE2PwlV2H2TIPnxao_c7KKrRdVsme9QPbYunLX9mHk8BJB2be-592__sLsI6Rpw</recordid><startdate>20010301</startdate><enddate>20010301</enddate><creator>Moon, S W</creator><creator>Kong, S G</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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subjects | Arrays Blocking Computer simulation Encoding Field programmable gate arrays Genetic algorithms Hardware Logic Mobile robots Neural networks Pattern classification Programmable logic arrays Reconfigurable logic Robot control Two dimensional |
title | Block-based neural networks |
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