A Cascade-Parallel Based Noise De-Embedding Technique for RF Modeling of CMOS Device

• Published in: IEEE microwave and wireless components letters 2011-08, Vol.21 (8), p.448-450
• Main Authors: Loo, X. S., Yeo, K. S., Chew, K. W. J., Chan, L. H. K., Ong, S. N., Do, M. A., Boon, C. C.
• Format: Article
• Language: English
• Subjects: Applied sciences; Cascades; Circuit properties; CMOS; CMOSFETs; Couplings; Design. Technologies. Operation analysis. Testing; Devices; Electric, optical and optoelectronic circuits; Electronics; Exact sciences and technology; Integrated circuit modeling; Integrated circuits; Mathematical models; Matrix converters; Metals; Microwave circuits, microwave integrated circuits, microwave transmission lines, submillimeter wave circuits; Microwave measurements; Microwaves; modeling; Noise; Noise levels; Noise measurement; Radio frequencies; semiconductor device noise; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
• ISSN: 1531-1309; 2771-957X; 1558-1764; 2771-9588
• DOI: 10.1109/LMWC.2011.2158533

In this letter, a unique cascade-parallel based noise de-embedding technique is presented for on-wafer device characterization and modeling. It utilizes two fully shielded THRU line structures and one OPEN structure that enable simultaneously de-embedding of series contact resistance, forward coupling and distributed parasitics of interconnect. Thus, it is more suitable for RF/millimeter wave noise characterization of lossy CMOS devices as compared to conventional lumped and cascade based de-embedding techniques. The proposed noise de-embedding technique is verified on both zero length THRU and OPEN devices. It demonstrates a better high frequency de-embedding performance than existing cascade based techniques by showing 1 dB improvement in predicted NFmin of 0.13 μm CMOS devices at 60 GHz. This is consistent with the further validation result on the de-embedded gain performance of the transistor.