Family of low-power truly modular programmable dividers in standard 0.35- mu m CMOS technology

A truly modular and power-scalable architecture for low-power programmable frequency dividers is presented. The architecture was used in the realization of a family of low-power fully programmable divider circuits, which consists of a 17-bit UHF divider, an 18-bit L-band divider, and a 12-bit refere...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2000-07, Vol.35 (7), p.1039-1045
Main Authors: Vaucher, Cicero S, Ferencic, Igor, Locher, Matthias, Sedvallson, Sebastian, Voegeli, Urs, Wang, Zhenhua
Format: Article
Language:English
Subjects:
Architecture
Circuits
CMOS
Dividers
Modular
Optimization
UHF
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Summary:A truly modular and power-scalable architecture for low-power programmable frequency dividers is presented. The architecture was used in the realization of a family of low-power fully programmable divider circuits, which consists of a 17-bit UHF divider, an 18-bit L-band divider, and a 12-bit reference divider. Key circuits of the architecture are 2/3 divider cells, which share the same logic and the same circuit implementation. The current consumption of each cell can be determined with a simple power optimization procedure. The implementation of the 2/3 divider cells is presented, the power optimization procedure is described, and the input amplifiers are briefly discussed. The circuits were processed in a standard 0.35 mu m bulk CMOS technology, and work with a nominal supply voltage of 2.2 V. The power efficiency of the UHF divider is 0.77 GHz/mW, and of the L-band divider, 0.57 GHz/mW. The measured input sensitivity is > 10 mVrms for the UHF divider, and > 20 mVrms for the L-band divider.
ISSN:0018-9200
DOI:10.1109/4.848214