SEU performance of TAG based flip-flops

We describe heavy-ion test results for two new single-event upset (SEU)-tolerant latches based on transition nand gates, one for single rail asynchronous and the other for dual rail synchronous designs, implemented in AMI 0.5 /spl mu/ process.

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Bibliographic Details
Published in:IEEE transactions on nuclear science 2005-12, Vol.52 (6), p.2550-2553
Main Authors: Shuler, R.L., Kouba, C., O'Neill, P.M.
Format: Article
Language:English
Subjects:
Circuits
Delay
FETs
Flip-flops
Gates
Inverters
Latches
Rails
Single event upset
Single-event effects
soft errors
Synchronous
Technical Activities Guide -TAG
Voting
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Description
Summary:We describe heavy-ion test results for two new single-event upset (SEU)-tolerant latches based on transition nand gates, one for single rail asynchronous and the other for dual rail synchronous designs, implemented in AMI 0.5 /spl mu/ process.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2005.860712