SEU performance of TAG based flip-flops

We describe heavy-ion test results for two new single-event upset (SEU)-tolerant latches based on transition nand gates, one for single rail asynchronous and the other for dual rail synchronous designs, implemented in AMI 0.5 /spl mu/ process.

Saved in:
Bibliographic Details
Published in:IEEE transactions on nuclear science 2005-12, Vol.52 (6), p.2550-2553
Main Authors: Shuler, R.L., Kouba, C., O'Neill, P.M.
Format: Article
Language:English
Subjects:
Circuits
Delay
FETs
Flip-flops
Gates
Inverters
Latches
Rails
Single event upset
Single-event effects
soft errors
Synchronous
Technical Activities Guide -TAG
Voting
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by cdi_FETCH-LOGICAL-c392t-e964bc6198973841e46fbf28710761f97bbd691582dc657485f7c0f9a97f76723
cites cdi_FETCH-LOGICAL-c392t-e964bc6198973841e46fbf28710761f97bbd691582dc657485f7c0f9a97f76723
container_end_page 2553
container_issue 6
container_start_page 2550
container_title IEEE transactions on nuclear science
container_volume 52
creator Shuler, R.L.
Kouba, C.
O'Neill, P.M.
description We describe heavy-ion test results for two new single-event upset (SEU)-tolerant latches based on transition nand gates, one for single rail asynchronous and the other for dual rail synchronous designs, implemented in AMI 0.5 /spl mu/ process.
doi_str_mv 10.1109/TNS.2005.860712
format article
fullrecord <record><control><sourceid>proquest_ieee_</sourceid><recordid>TN_cdi_proquest_miscellaneous_914660528</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1589237</ieee_id><sourcerecordid>2543243921</sourcerecordid><originalsourceid>FETCH-LOGICAL-c392t-e964bc6198973841e46fbf28710761f97bbd691582dc657485f7c0f9a97f76723</originalsourceid><addsrcrecordid>eNp9kE1LAzEQhoMoWKtnD14WD_a0bSabrzkWqVUoemh7DrvbBLZsmzVpD_57s6wgePAyw8DzDjMPIfdApwAUZ5v39ZRRKqZaUgXsgoxACJ2DUPqSjCgFnSNHvCY3Me7TyAUVIzJZL7ZZZ4Pz4VAea5t5l23my6wqo91lrm263LW-i7fkypVttHc_fUy2L4vN82u--li-Pc9XeV0gO-UWJa9qCahRFZqD5dJVjmkFVElwqKpqJxGEZrtaCsW1cKqmDktUTknFijGZDHu74D_PNp7MoYm1bdvyaP05GgQuJRVMJ_LpX5JpKmQqCXz8A-79ORzTF2lbf6nmPTQboDr4GIN1pgvNoQxfBqjp_Zrk1_R-zeA3JR6GRGOt_aWFRlao4hvgn3In</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>911989840</pqid></control><display><type>article</type><title>SEU performance of TAG based flip-flops</title><source>IEEE Xplore (Online service)</source><creator>Shuler, R.L. ; Kouba, C. ; O'Neill, P.M.</creator><creatorcontrib>Shuler, R.L. ; Kouba, C. ; O'Neill, P.M.</creatorcontrib><description>We describe heavy-ion test results for two new single-event upset (SEU)-tolerant latches based on transition nand gates, one for single rail asynchronous and the other for dual rail synchronous designs, implemented in AMI 0.5 /spl mu/ process.</description><identifier>ISSN: 0018-9499</identifier><identifier>EISSN: 1558-1578</identifier><identifier>DOI: 10.1109/TNS.2005.860712</identifier><identifier>CODEN: IETNAE</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Circuits ; Delay ; FETs ; Flip-flops ; Gates ; Inverters ; Latches ; Rails ; Single event upset ; Single-event effects ; soft errors ; Synchronous ; Technical Activities Guide -TAG ; Voting</subject><ispartof>IEEE transactions on nuclear science, 2005-12, Vol.52 (6), p.2550-2553</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2005</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c392t-e964bc6198973841e46fbf28710761f97bbd691582dc657485f7c0f9a97f76723</citedby><cites>FETCH-LOGICAL-c392t-e964bc6198973841e46fbf28710761f97bbd691582dc657485f7c0f9a97f76723</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1589237$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,777,781,27905,27906,54777</link.rule.ids></links><search><creatorcontrib>Shuler, R.L.</creatorcontrib><creatorcontrib>Kouba, C.</creatorcontrib><creatorcontrib>O'Neill, P.M.</creatorcontrib><title>SEU performance of TAG based flip-flops</title><title>IEEE transactions on nuclear science</title><addtitle>TNS</addtitle><description>We describe heavy-ion test results for two new single-event upset (SEU)-tolerant latches based on transition nand gates, one for single rail asynchronous and the other for dual rail synchronous designs, implemented in AMI 0.5 /spl mu/ process.</description><subject>Circuits</subject><subject>Delay</subject><subject>FETs</subject><subject>Flip-flops</subject><subject>Gates</subject><subject>Inverters</subject><subject>Latches</subject><subject>Rails</subject><subject>Single event upset</subject><subject>Single-event effects</subject><subject>soft errors</subject><subject>Synchronous</subject><subject>Technical Activities Guide -TAG</subject><subject>Voting</subject><issn>0018-9499</issn><issn>1558-1578</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2005</creationdate><recordtype>article</recordtype><recordid>eNp9kE1LAzEQhoMoWKtnD14WD_a0bSabrzkWqVUoemh7DrvbBLZsmzVpD_57s6wgePAyw8DzDjMPIfdApwAUZ5v39ZRRKqZaUgXsgoxACJ2DUPqSjCgFnSNHvCY3Me7TyAUVIzJZL7ZZZ4Pz4VAea5t5l23my6wqo91lrm263LW-i7fkypVttHc_fUy2L4vN82u--li-Pc9XeV0gO-UWJa9qCahRFZqD5dJVjmkFVElwqKpqJxGEZrtaCsW1cKqmDktUTknFijGZDHu74D_PNp7MoYm1bdvyaP05GgQuJRVMJ_LpX5JpKmQqCXz8A-79ORzTF2lbf6nmPTQboDr4GIN1pgvNoQxfBqjp_Zrk1_R-zeA3JR6GRGOt_aWFRlao4hvgn3In</recordid><startdate>20051201</startdate><enddate>20051201</enddate><creator>Shuler, R.L.</creator><creator>Kouba, C.</creator><creator>O'Neill, P.M.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7QF</scope><scope>7QL</scope><scope>7QQ</scope><scope>7SC</scope><scope>7SE</scope><scope>7SP</scope><scope>7SR</scope><scope>7T7</scope><scope>7TA</scope><scope>7TB</scope><scope>7U5</scope><scope>7U9</scope><scope>8BQ</scope><scope>8FD</scope><scope>C1K</scope><scope>F28</scope><scope>FR3</scope><scope>H8D</scope><scope>H94</scope><scope>JG9</scope><scope>JQ2</scope><scope>KR7</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope><scope>M7N</scope><scope>P64</scope></search><sort><creationdate>20051201</creationdate><title>SEU performance of TAG based flip-flops</title><author>Shuler, R.L. ; Kouba, C. ; O'Neill, P.M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c392t-e964bc6198973841e46fbf28710761f97bbd691582dc657485f7c0f9a97f76723</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2005</creationdate><topic>Circuits</topic><topic>Delay</topic><topic>FETs</topic><topic>Flip-flops</topic><topic>Gates</topic><topic>Inverters</topic><topic>Latches</topic><topic>Rails</topic><topic>Single event upset</topic><topic>Single-event effects</topic><topic>soft errors</topic><topic>Synchronous</topic><topic>Technical Activities Guide -TAG</topic><topic>Voting</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Shuler, R.L.</creatorcontrib><creatorcontrib>Kouba, C.</creatorcontrib><creatorcontrib>O'Neill, P.M.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998–Present</collection><collection>IEEE/IET Electronic Library</collection><collection>CrossRef</collection><collection>Aluminium Industry Abstracts</collection><collection>Bacteriology Abstracts (Microbiology B)</collection><collection>Ceramic Abstracts</collection><collection>Computer and Information Systems Abstracts</collection><collection>Corrosion Abstracts</collection><collection>Electronics &amp; Communications Abstracts</collection><collection>Engineered Materials Abstracts</collection><collection>Industrial and Applied Microbiology Abstracts (Microbiology A)</collection><collection>Materials Business File</collection><collection>Mechanical &amp; Transportation Engineering Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Virology and AIDS Abstracts</collection><collection>METADEX</collection><collection>Technology Research Database</collection><collection>Environmental Sciences and Pollution Management</collection><collection>ANTE: Abstracts in New Technology &amp; Engineering</collection><collection>Engineering Research Database</collection><collection>Aerospace Database</collection><collection>AIDS and Cancer Research Abstracts</collection><collection>Materials Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Civil Engineering Abstracts</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts – Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><collection>Algology Mycology and Protozoology Abstracts (Microbiology C)</collection><collection>Biotechnology and BioEngineering Abstracts</collection><jtitle>IEEE transactions on nuclear science</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Shuler, R.L.</au><au>Kouba, C.</au><au>O'Neill, P.M.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>SEU performance of TAG based flip-flops</atitle><jtitle>IEEE transactions on nuclear science</jtitle><stitle>TNS</stitle><date>2005-12-01</date><risdate>2005</risdate><volume>52</volume><issue>6</issue><spage>2550</spage><epage>2553</epage><pages>2550-2553</pages><issn>0018-9499</issn><eissn>1558-1578</eissn><coden>IETNAE</coden><abstract>We describe heavy-ion test results for two new single-event upset (SEU)-tolerant latches based on transition nand gates, one for single rail asynchronous and the other for dual rail synchronous designs, implemented in AMI 0.5 /spl mu/ process.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TNS.2005.860712</doi><tpages>4</tpages><oa>free_for_read</oa></addata></record>
fulltext fulltext
identifier ISSN: 0018-9499
ispartof IEEE transactions on nuclear science, 2005-12, Vol.52 (6), p.2550-2553
issn 0018-9499
1558-1578
language eng
recordid cdi_proquest_miscellaneous_914660528
source IEEE Xplore (Online service)
subjects Circuits
Delay
FETs
Flip-flops
Gates
Inverters
Latches
Rails
Single event upset
Single-event effects
soft errors
Synchronous
Technical Activities Guide -TAG
Voting
title SEU performance of TAG based flip-flops
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-19T09%3A44%3A31IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_ieee_&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=SEU%20performance%20of%20TAG%20based%20flip-flops&rft.jtitle=IEEE%20transactions%20on%20nuclear%20science&rft.au=Shuler,%20R.L.&rft.date=2005-12-01&rft.volume=52&rft.issue=6&rft.spage=2550&rft.epage=2553&rft.pages=2550-2553&rft.issn=0018-9499&rft.eissn=1558-1578&rft.coden=IETNAE&rft_id=info:doi/10.1109/TNS.2005.860712&rft_dat=%3Cproquest_ieee_%3E2543243921%3C/proquest_ieee_%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c392t-e964bc6198973841e46fbf28710761f97bbd691582dc657485f7c0f9a97f76723%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=911989840&rft_id=info:pmid/&rft_ieee_id=1589237&rfr_iscdi=true