A 10-Gb/s 16:1 multiplexer and 10-GHz clock synthesizer in 0.25-μm SiGe BiCMOS

A 10-Gb/s 16:1 multiplexer, 10-GHz clock generator phase-locked loop (PLL), and 6 x 16 b input data buffer are integrated in a 0.25- mu m SiGe BiCMOS technology. The chip multiplexes 16 parallel input data streams each at 622 Mb/s into a 9.953-Gb/s serial output stream. The device also produces a 9....

Full description

Saved in:
Bibliographic Details
Published in:IEEE journal of solid-state circuits 2001-12, Vol.36 (12), p.1946-1953
Main Authors: Hong-Ih Cong, Logan, S.M., Loinaz, M.J., O'Brien, K.J., Perry, E.E., Polhemus, G.D., Scoggins, J.E., Snowdon, K.P., Ward, M.G.
Format: Article
Language:English
Subjects:
Buffers
Chips
Clock generators
Clocks
Jitter
Multiplexing
Silicon germanides
Streams
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A 10-Gb/s 16:1 multiplexer, 10-GHz clock generator phase-locked loop (PLL), and 6 x 16 b input data buffer are integrated in a 0.25- mu m SiGe BiCMOS technology. The chip multiplexes 16 parallel input data streams each at 622 Mb/s into a 9.953-Gb/s serial output stream. The device also produces a 9.953-GHz output clock from a 622- or 155-MHz reference frequency. The on-board 10-GHz voltage-controlled oscillator (VCO) has a plus or minus 10% tuning range allowing the chip to accommodate both the SONET/SDH data rate of 9.953 Gb/s and a forward error correction coding rate of 10.664 Gb/s. The 6 x 16 b input data buffer accommodates plus or minus 2.4 ns of parallel input data phase drift at 622 Mb/s. A delay-locked loop (DLL) in the input data buffer allows the support of multiple input clocking models. Using a clock generator PLL bandwidth of 6 MHz, the 9.953-GHz output clock exhibits a generated jitter of less than 0.05 UI sub(P-P) over a 50-kHz to 80-MHz bandwidth and jitter peaking of less than 0.05 dB.
ISSN:0018-9200
DOI:10.1109/4.972145