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An iterative cutting procedure for determining the optimal wafer exposure pattern

Conventionally, people focus on defect reduction to improve yield rate. Little research has been done to deal with the problem of optimizing wafer exposure patterns. This paper develops a computer-based procedure to maximize the number of dies possibly produced from a wafer. A program has been devel...

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Published in:	IEEE transactions on semiconductor manufacturing 1999-08, Vol.12 (3), p.375-377
Main Authors:	CHIEN, C.-F, HSU, S.-C, CHEN, C.-P
Format:	Article
Language:	English
Subjects:	Applied sciences Costs Councils Cutting Electronics Exact sciences and technology Expert systems Fabrication Factories Industrial engineering Investments Iterative methods Microelectronic fabrication (materials and surfaces technology) Optimization Optimization methods Plants Production facilities Sawing Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Semiconductors Shape Upper bound Wafers
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container_title	IEEE transactions on semiconductor manufacturing
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creator	CHIEN, C.-F HSU, S.-C CHEN, C.-P
description	Conventionally, people focus on defect reduction to improve yield rate. Little research has been done to deal with the problem of optimizing wafer exposure patterns. This paper develops a computer-based procedure to maximize the number of dies possibly produced from a wafer. A program has been developed and implemented in a 6-in wafer fabrication factory in Taiwan. The results validate the practical viability of the proposed procedure.
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source	IEEE Electronic Library (IEL) Journals
subjects	Applied sciences Costs Councils Cutting Electronics Exact sciences and technology Expert systems Fabrication Factories Industrial engineering Investments Iterative methods Microelectronic fabrication (materials and surfaces technology) Optimization Optimization methods Plants Production facilities Sawing Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Semiconductors Shape Upper bound Wafers
title	An iterative cutting procedure for determining the optimal wafer exposure pattern
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