A pixel-parallel image processor using logic pitch-matched to dynamic memory

A pixel-parallel image processor provides the capability for desktop systems to perform low-level image processing tasks in real time. Compact logic units are pitch-matched to DRAM columns to form dense blocks of processing elements. The processing elements are interconnected to form a 64/spl times/...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1999-06, Vol.34 (6), p.831-839, Article 831
Main Authors: Gealow, J.C., Sodini, C.G.
Format: Article
Language:English
Subjects:
Clocks
Devices
Dynamics
Image processing
Image processors
Logic
Logic arrays
Logic devices
Multiprocessor interconnection networks
Pixel
Random access memory
Real time
Real time systems
Registers
Signal generators
Tasks
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Summary:A pixel-parallel image processor provides the capability for desktop systems to perform low-level image processing tasks in real time. Compact logic units are pitch-matched to DRAM columns to form dense blocks of processing elements. The processing elements are interconnected to form a 64/spl times/64 array, with each processing element assigned to a single pixel. Operating with a 60-ns clock cycle in a complete system, fully functional devices dissipate 300 mW. Using the devices, low-level image processing tasks have been performed in real time with input images provided at rates exceeding 30 frames/s.
ISSN:0018-9200
1558-173X
DOI:10.1109/4.766817