A 100-MHz, 16-b, direct digital frequency synthesizer with a 100-dBc spurious-free dynamic range

This paper describes the architecture and the IC implementation of a direct digital frequency synthesizer (DDFS) that is based on an angle rotation algorithm (similar to CORDIC). It is shown that the architecture can be implemented as a multiplierless, feedforward, and easily pipelineable datapath....

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1999-08, Vol.34 (8), p.1034-1043
Main Authors: Madisetti, A., Kwentus, A.Y., Willson, A.N.
Format: Article
Language:English
Subjects:
Architecture
CMOS
CMOS integrated circuits
Digital
Digital integrated circuits
Dynamic range
Frequency control
Frequency synthesizers
Integrated circuit synthesis
Integrated circuit testing
Integrated circuits
Prototypes
Sampling
Sampling methods
Tuning
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Summary:This paper describes the architecture and the IC implementation of a direct digital frequency synthesizer (DDFS) that is based on an angle rotation algorithm (similar to CORDIC). It is shown that the architecture can be implemented as a multiplierless, feedforward, and easily pipelineable datapath. A prototype IC has been designed, fabricated in 1.0-/spl mu/m CMOS, and tested. The IC produces 16-b sine and cosine outputs with a spurious-free dynamic range of more than 100 dBc. A 36-b frequency control word gives a tuning resolution of 0.0015 Hz at a 100-MHz sampling rate.
ISSN:0018-9200
1558-173X
DOI:10.1109/4.777100