High-voltage-tolerant I/O buffers with low-voltage CMOS process

This paper presents high-voltage-tolerant I/O buffer designs for a 1.9-V external cache interface and a 3.3-V system interface using 1.9-V MOS transistors in a 0.21-/spl mu/m process with 40-/spl Aring/ gate-oxide thickness. Various circuit techniques are used for 1.9- and 3.3-V I/O buffers to ensur...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1999-11, Vol.34 (11), p.1512-1525
Main Authors: Singh, G.P., Salem, R.B.
Format: Article
Language:English
Subjects:
Bonding
Buffers
Circuits
CMOS process
Design engineering
Driver circuits
Electric potential
Leakage current
Metal oxide semiconductors
MOS devices
MOSFETs
Power supplies
Semiconductor devices
Steady-state
Stress
Transistors
Voltage
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Summary:This paper presents high-voltage-tolerant I/O buffer designs for a 1.9-V external cache interface and a 3.3-V system interface using 1.9-V MOS transistors in a 0.21-/spl mu/m process with 40-/spl Aring/ gate-oxide thickness. Various circuit techniques are used for 1.9- and 3.3-V I/O buffers to ensure that the voltage across the gate oxide of every MOS element is below specified limits of 2.2 V for transient (short duty cycle) and 1.9 V for steady state. Only one PMOS pullup driver transistor between the bond pad and the power supply, and one NMOS pulldown driver transistor between the bond pad and ground, are used for the 1.9-V I/O buffer design, while cascoded MOS transistors between the bond pad and power supply or ground terminals are used for the 3.3-V I/O buffer design. The primary design goal is to ensure the reliability of MOS elements by avoiding excessive gate oxide stress due to high electric fields. However, due to differences in requirements for speed, power-supply voltage, and tristate leakage current, completely different circuit techniques have been used for the two designs. Both of the designs have been successfully implemented in a 400-MHz UltraSPARC microprocessor.
ISSN:0018-9200
1558-173X
DOI:10.1109/4.799855