Parametric yield formulation of MOS IC's affected by mismatch effect

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems 1999-05, Vol.18 (5), p.582-596
• Main Authors: Conti, M., Crippa, P., Orcioni, S., Turchetti, C.
• Format: Article
• Language: English
• Subjects: Applied sciences; Approximation; Autocorrelation; Circuit design; CMOS technology; Computer aided design; Computer science; control theory; systems; Covariance matrix; Design engineering; Devices; Electric, optical and optoelectronic circuits; Electronics; Exact sciences and technology; Integrated circuit modeling; Integrated circuit technology; Integrated circuit yield; Integrated circuits; Manufacturing; Mathematical models; Predictive models; Software; Stochastic processes; Theoretical study. Circuits analysis and design; Very large scale integration
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/43.759074

A rigorous formulation of the parametric yield for very large scale integration (VLSI) designs including the mismatch effect is proposed. The theory has been carried out starting from a general statistical model relating random variations of device parameters to the stochastic behavior of process parameters. The model predicts a dependence of correlation, between devices fabricated in the same die, on their dimensions and mutual distances so that mismatch between equally designed devices can be considered as a particular case of such a model. As an application example, a new model for the autocorrelation function is proposed from which the covariance matrix of the parameters is derived. By assuming a linear approximation, a suitable formulation of the parametric yield for VLSI circuit design is obtained in terms of the covariance matrix of parameters.