Stress induced defects and transistor leakage for shallow trench isolated SOI

Anomalous leakage currents are observed for shallow trench isolated SOI transistors. The leakage effect is caused by stress induced dislocations in the device silicon islands. These dislocations are observed using cross-sectional TEM analysis. For the shallow trench isolation process employed, the l...

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Bibliographic Details
Published in:IEEE electron device letters 1999-05, Vol.20 (5), p.248-250
Main Authors: Sleight, J.W., Chnan Lin, Grula, G.J.
Format: Article
Language:English
Subjects:
CMOS technology
Defects
Devices
Dislocations
Fabrication
Implants
Isolation technology
Leakage
Leakage current
MOSFET circuits
Oxidation
Robustness
Semiconductor devices
Silicon on insulator technology
Stress
Stresses
Transistors
Trenches
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Summary:Anomalous leakage currents are observed for shallow trench isolated SOI transistors. The leakage effect is caused by stress induced dislocations in the device silicon islands. These dislocations are observed using cross-sectional TEM analysis. For the shallow trench isolation process employed, the leakage is most pronounced on SIMOX wafers when the buried oxide thickness is scaled down to 100 nm. Limiting fabrication stresses to a minimum is critical for eliminating this leakage defect and in obtaining a robust, high yielding SOI STI process.
ISSN:0741-3106
1558-0563
DOI:10.1109/55.761029