Loading…

Performance of thin pixel sensors irradiated up to a fluence of and development of a new interconnection technology for the upgrade of the ATLAS pixel system

A new pixel module concept is presented, where thin sensors and a novel vertical integration technique are combined. This R&D activity is carried out in view of the ATLAS pixel detector upgrades. A first set of n-in-p pixel sensors with active thicknesses of 75 and [inline image][inline image] h...

Full description

Saved in:
Bibliographic Details
Published in:Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment Accelerators, spectrometers, detectors and associated equipment, 2011-09, Vol.650 (1), p.145-149
Main Authors: Macchiolo, A., Andricek, L., Beimforde, M., Moser, H.-G., Nisius, R., Richter, R.H., Weigell, P.
Format: Article
Language:English
Subjects:
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A new pixel module concept is presented, where thin sensors and a novel vertical integration technique are combined. This R&D activity is carried out in view of the ATLAS pixel detector upgrades. A first set of n-in-p pixel sensors with active thicknesses of 75 and [inline image][inline image] has been produced using a thinning technique developed at the Max-Planck-Institut Halbleiterlabor (HLL). Charge Collection Efficiency measurements have been performed, yielding a higher CCE than expected from the present radiation damage models. The interconnection of thin n-in-p pixels to the FE-I3 ATLAS electronics is under way, exploiting the Solid Liquid Interdiffusion (SLID) technique developed by the Fraunhofer Institut EMFT. In addition, preliminary studies aimed at Inter-Chip-Vias (ICV) etching into the FE-I3 electronics are reported. ICVs will be used to route the signals vertically through the read-out chip, to newly created pads on the backside. This should serve as a proof of principle for future four-side tileable pixel assemblies, avoiding the cantilever presently needed in the chip for the wire bonding.
ISSN:0168-9002
DOI:10.1016/j.nima.2010.11.163