Design Issues and Implementations for Floating-Point Divide-Add Fused

This brief presents a dedicated unit for the combined operation of floating-point (FP) division followed by addition/subtraction-the divide-add fused (DAF). The goal of this unit is to increase the performance and the accuracy of applications where this combined operation is frequent, such as the in...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2010-04, Vol.57 (4), p.295-299
Main Authors: Amaricai, Alexandru, Vladutiu, Mircea, Boncalo, Oana
Format: Article
Language:English
Subjects:
Accuracy
Approximation
Circuits
Computer arithmetic
Costs
Delay
Design engineering
digit-recurrence algorithms
Digital arithmetic
Digital signal processors
divide-add fused (DAF)
Dividers
Energy consumption
Filled plastics
Floating point arithmetic
floating-point (FP) arithmetic
Hardware
Mathematical analysis
Nonlinear equations
Polynomials
Quotients
Signal processing algorithms
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Summary:This brief presents a dedicated unit for the combined operation of floating-point (FP) division followed by addition/subtraction-the divide-add fused (DAF). The goal of this unit is to increase the performance and the accuracy of applications where this combined operation is frequent, such as the interval Newton's method or the polynomial approximation. The proposed DAF unit presents a similar architecture to the FP multiply-accumulate units. The main difference is represented by the divider, which is implemented using digit-recurrence algorithms. An important design tradeoff regarding DAF is represented by the number of required quotient bits. We present the impact of the adopted number of quotient bits on accuracy, cost, and performance. Consequently, two implementations are proposed: one pro-accuracy and one pro-performance. We show that the proposed implementations have better accuracy with respect to the solution based on two distinct units: an FP divider and an FP adder. The implementation suitable for lower latency presents the best cost-performance tradeoff.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2010.2043473