A dynamic quality-adjustable H.264 intra coder

This paper presents a flexible qualityadjustable H.264 intra frame encoder for power aware video applications. Encapsulating a reconfigurable algorithm, the proposed design can configure the encoding search algorithm to operate at different quality modes with the design tradeoff between video qualit...

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Bibliographic Details
Published in:IEEE transactions on consumer electronics 2011-08, Vol.57 (3), p.1203-1211
Main Authors: Chen, Jia-wei, Chang, Hsiu-cheng, Wang, Jinn-shyan, Guo, Jiun-in
Format: Article
Language:English
Subjects:
Algorithm design and analysis
Algorithms
Clustering algorithms
CMOS
Coders
Electronics
Encoders
Encoding
H.264 Intra Frame Coder
Hardware
Heuristic algorithms
Optimization
Power consumption
Prediction algorithms
Quality-Adjustable Encoding
Streaming media
Video Encoding
VLSI Architecture
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Summary:This paper presents a flexible qualityadjustable H.264 intra frame encoder for power aware video applications. Encapsulating a reconfigurable algorithm, the proposed design can configure the encoding search algorithm to operate at different quality modes with the design tradeoff between video quality and power consumption. In addition, some timing optimization schemes are proposed to increase the hardware throughput of the proposed design to encode H.264 intra video sequences on D1, HD720 and HD1080 with 10 mW to 16 mW, 27 mW to 45 mW, and 60 mW power consumption under different quality modes, respectively. Implemented by using a 90nm CMOS technology, the proposed design comprises 91 kgates and 2.9 kB internal memory.
ISSN:0098-3063
1558-4127
DOI:10.1109/TCE.2011.6018875