High efficient distributed video coding with parallelized design for LDPCA decoding on CUDA based GPGPU

Distributed video coding (DVC) is a new coding paradigm targeting on applications with the need of low-complexity and/or low-power encoding at the cost of a high-complexity decoding. In the DVC architectures based on Error Control Codes (ECCs) with a feedback channel, the high decoding complexity co...

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Bibliographic Details
Published in:Journal of visual communication and image representation 2012, Vol.23 (1), p.63-74
Main Authors: Pai, Yu-Shan, Shen, Yun-Chung, Wu, Ja-Ling
Format: Article
Language:English
Subjects:
Accumulated parity check matrix
Algorithms
Architecture
Coding
Computation
CUDA
Decoding
Density
Distributed video coding (DVC)
Gain
General Purpose Graphics Processing Unit (GPGPU)
Ladder Step Size Request (LSSR)
LDPC Accumulate (LDPCA)
Slepian-Wolf
Wyner-Ziv
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Summary:Distributed video coding (DVC) is a new coding paradigm targeting on applications with the need of low-complexity and/or low-power encoding at the cost of a high-complexity decoding. In the DVC architectures based on Error Control Codes (ECCs) with a feedback channel, the high decoding complexity comes from the decode-check-request iterations between the ECC encoder and the ECC decoder. In this paper, a parallel message-passing decoding algorithm for computing low density parity check (LDPC) syndromes is applied through the Compute Unified Device Architecture (CUDA) based on General Purpose Graphics Processing Unit (GPGPU). Furthermore, we proposed a novel rate control mechanism, dubbed as the Ladder Step Size Request (LSSR), to reduce the number of requests which leads to much speedup gain. Experimental results show that, through our work, the overall DVC decoding speedup gain can reach 46.52 with only 0.2 dB rate distortion performance loss.
ISSN:1047-3203
1095-9076
DOI:10.1016/j.jvcir.2011.08.004