Low-Power Artificial Neural Network Perceptron Based on Monolayer MoS2

• Published in: ACS nano 2022-03, Vol.16 (3), p.3684-3694
• Main Authors: Migliato Marega, Guilherme, Wang, Zhenyu, Paliy, Maksym, Giusi, Gino, Strangio, Sebastiano, Castiglione, Francesco, Callegari, Christian, Tripathi, Mukesh, Radenovic, Aleksandra, Iannaccone, Giuseppe, Kis, Andras
• Format: Article
• Language: English
• ISSN: 1936-0851; 1936-086X
• DOI: 10.1021/acsnano.1c07065

Machine learning and signal processing on the edge are poised to influence our everyday lives with devices that will learn and infer from data generated by smart sensors and other devices for the Internet of Things. The next leap toward ubiquitous electronics requires increased energy efficiency of processors for specialized data-driven applications. Here, we show how an in-memory processor fabricated using a two-dimensional materials platform can potentially outperform its silicon counterparts in both standard and nontraditional Von Neumann architectures for artificial neural networks. We have fabricated a flash memory array with a two-dimensional channel using wafer-scale MoS2. Simulations and experiments show that the device can be scaled down to sub-micrometer channel length without any significant impact on its memory performance and that in simulation a reasonable memory window still exists at sub-50 nm channel lengths. Each device conductance in our circuit can be tuned with a 4-bit precision by closed-loop programming. Using our physical circuit, we demonstrate seven-segment digit display classification with a 91.5% accuracy with training performed ex situ and transferred from a host. Further simulations project that at a system level, the large memory arrays can perform AlexNet classification with an upper limit of 50 000 TOpS/W, potentially outperforming neural network integrated circuits based on double-poly CMOS technology.