An optimized fir filter design for phase based processing using verilog HDL

For an adaptive FIR filter, a new approximation DA architecture is suggested. The weights of the filter are updated using the LMS algorithm. To increase the area and power efficiency of the filter, we merged the CSD number with the DA approach in this architecture. The DA computation is done without...

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Bibliographic Details
Main Authors: Mamidala, Vijay Karthik, Qureshi, Vaseem Ahmed
Format: Conference Proceeding
Language:English
Subjects:
Algorithms
Computation
Design optimization
Filter design (mathematics)
FIR filters
Power efficiency
Power management
Online Access:Get full text
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Description
Summary:For an adaptive FIR filter, a new approximation DA architecture is suggested. The weights of the filter are updated using the LMS algorithm. To increase the area and power efficiency of the filter, we merged the CSD number with the DA approach in this architecture. The DA computation is done without the use of a LUT. Instead, DA computation is done using registers. The partial products are added using the Wallace tree adder, which increases the filter’s speed while reducing its complexity. The structure’s device utilization data shows that the area and power efficiency are both better than earlier designs. The proposed structure is generated in Verilog and implemented in a Virtex FPGA device.
ISSN:0094-243X
1551-7616
DOI:10.1063/5.0125229