Design of unsigned 2n+1 parallel residue arithmetic multiplier

Residue Multiplication operations are extensively used in Residue Number System (RNS) based cryptosystem architecture. Pointing to increase the speed performance of RNS crypto processors, the new parallel unsigned 2n+1 residue multiplier is designed in this work. Mathematical model, Algorithm, Archi...

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Bibliographic Details
Published in:AIP conference proceedings 2023-04, Vol.2725 (1)
Main Authors: Elango, S., Sampath, P., Philip, Sajan P., Raj, A. Daniel
Format: Article
Language:English
Subjects:
Algorithms
Application specific integrated circuits
Multiplication
Multipliers
Residue number systems
Online Access:Get full text
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Summary:Residue Multiplication operations are extensively used in Residue Number System (RNS) based cryptosystem architecture. Pointing to increase the speed performance of RNS crypto processors, the new parallel unsigned 2n+1 residue multiplier is designed in this work. Mathematical model, Algorithm, Architecture and FPGA implementation is done in this work. The proposed residue multiplier is described in Verilog HDL and synthesized in Application-Specific Integrated Circuits (ASIC) environment. Cadence RTL Compiler estimates the Area, Power and Delay performance parameters using various CMOS libraries. The proposed 2n+1 residue multiplication scheme saves 13% of the area, improves the speed by 19% and PDP by 23% compared to the recent 2n+1 residue multipliers.
ISSN:0094-243X
1551-7616
DOI:10.1063/5.0125244