Performance evaluation of the two-stage CNFET operational amplifier at 32 nm and 10 nm technology nodes

• Main Authors: Chua, W. H., Uttraphan, C., Kok, B. C., Ahmad, N.
• Format: Conference Proceeding
• Language: English
• Subjects: Carbon nanotubes; CMOS; Current carriers; Design optimization; Electronic properties; Field effect transistors; Integrated circuits; Leakage current; Operational amplifiers; Performance degradation; Performance evaluation; Rejection; Semiconductor devices
• ISSN: 0094-243X; 1551-7616
• DOI: 10.1063/5.0144302

Complementary metal-oxide-semiconductor (CMOS) technology is a dominant technology adopted in the manufacturing of integrated circuits (IC) for decades. When the technology is scaled below 5 nm, the challenges such as the short-channel effect, source-to-drain tunnelling, leakage current, and hot carrier will become more significant in terms of performance degradation. The carbon nanotube field-effect transistor (CNFET) device is the most suitable device as an alternative to the metal-oxide semiconductor field-effect transistor (MOSFET) due to their similarity of the structure and electronic properties. In this paper, the optimized design of the 32 nm and 10 nm two-stage CNFET op-amps are evaluated, analysed, and compared. Simulation results indicate that the optimized 10 nm circuit possess higher unity-gain bandwidth (UGB), open-loop gain, and common-mode rejection ratio (CMRR) as compared to 32 nm at the cost of the power supply rejection ratio (PSRR), phase margin, input common mode voltage range (ICMR), and output resistance.