Emerging trends in network on chip design for low latency and enhanced throughput applications

• Main Authors: Mulajkar, Ashish, Sinha, Sanjeet K., Patel, Govind Singh
• Format: Conference Proceeding
• Language: English
• Subjects: Buffers; Communication; Embedded systems; Network latency; Power management; Routers; System on chip
• ISSN: 0094-243X; 1551-7616
• DOI: 10.1063/5.0162952

Traditionally Bus is used as an interconnection mechanism in many embedded systems. The Bus often fails to accommodate the communication needs of such systems, as the need for extensive processing rises. The Bus cannot scale well. NoCs offer scalable communication solutions, serving as a replacement to the traditional Bus based interconnections. NoC has common limitations of area occupancy and static power analysis as buffers are used in the design of architecture. Hence buffer-less routing techniques can be used to overcome the limitations. The initiation of a bus in NoC architecture reduces the throughput of the system. The basic components used in NoC design are NI (Network Interface), links, and routers. Bus structures in NoC can be replaced with various device elements to overcome communication errors. In this paper study of advanced concepts in NoC design are discussed which is Multi drop links, three-dimensional NoC, RF Interconnect, Nano -Photonic NoC, and Wireless NoC. Also, analysis is made among routers for low power and latency applications. The evaluation shows that compared to the baseline bus-based SoC the NoC-based system improves communication latency from 44% up to 97% while resulting in 1.68 × −37.5× higher throughput. Xilinx ISE 14.7 tool along with Verilog codes is used for simulating the architecture.