Electrical characterization of dry and wet processed interface layer in Ge/High-K devices

• Published in: Journal of vacuum science and technology. B, Nanotechnology & microelectronics Nanotechnology & microelectronics, 2016-03, Vol.34 (2)
• Main Authors: Ding, Y. M., Misra, D., Bhuyian, M. N., Tapily, Kandabara, Clark, Robert D., Consiglio, Steve, Wajda, Cory S., Leusink, Gert J.
• Format: Article
• Language: English
• ISSN: 2166-2746; 2166-2754
• DOI: 10.1116/1.4943559

In this work, the dry and wet processed interface layers for three different p type Ge/atomic layer deposition (ALD) 1 nm-Al2O3/ALD 3.5 nm-ZrO2/ALD TiN gate stacks on 300 mm wafers were studied at low temperatures by capacitance–voltage (CV), conductance–voltage measurement, and deep level transient spectroscopy. The interface treatments were (1) simple chemical oxidation (Chemox); (2) chemical oxide removal (COR) followed by 1 nm oxide by slot-plane-antenna (SPA) plasma (COR and SPAOx); and (3) COR followed by vapor O3 treatment (COR and O3). Since low temperature measurements are more reliable, several parameters like equivalent oxide thickness, flatband voltage, bulk doping, and surface potential as a function of gate voltage are reported. Different temperature CV measurement suggests that all the samples are pinned at flat band voltage (C it give a pseudoaccumulation region) due to large D it (larger than 1013 cm−2/eV). Room temperature measurement indicates that superior results were observed for slot-plane-plasma-oxidation processed samples.