Implementing the open master hearing aid on a system-on-chip field programmable gate array

• Published in: The Journal of the Acoustical Society of America 2020-10, Vol.148 (4), p.2508-2508
• Main Authors: Snider, Ross, Blunt, Matthew, Vannoy, Trevor, Sobrero, Dustin, Wickham, Dylan, Davis, Tyler
• Format: Article
• Language: English
• ISSN: 0001-4966; 1520-8524
• DOI: 10.1121/1.5146971

System-on-Chip (SoC) Field Programmable Gate Arrays (FPGAs) are ideal for embedded real-time signal processing because of their high performance and low latency. Here we describe the process of implementing the Open Master Hearing Aid [1] on an SoC FPGA. We started by creating a FFT based Simulink model to implement hardware friendly frequency-domain processing. This model implements Short-Time Fourier Transform processing in an overlap-and-add architecture. This was followed by porting additional openMHA processing blocks, such as dynamic range compression, to Simulink. Once the hearing aid Simulink model was finished, Mathwork's HDL Coder was used to create VHDL. To create an interactive system, we used Audio Logic's code generation tools to generate the infrastructure needed to communicate with the hearing aid processor in real-time; this includes generating device drivers that allow Linux to communicate with the hearing aid processor, as well as a custom web application with an autogenerated GUI. This example provides an open reference design for those who may be interested in low latency FPGA based data flow architectures. 1. www.openmha.org