An integration approach for graphene double-gate transistors

In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for microelectronics integration: bottom gates with ultra-thin (2nm) high-quality thermally grown SiO 2 dielectrics, shallow trench isolati...

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Bibliographic Details
Main Authors: Vaziri, S., Smith, A. D., Henkel, C., Ostling, M., Lemme, M. C., Lupina, G., Lippert, G., Dabrowski, J., Mehr, W.
Format: Conference Proceeding
Language:English
Subjects:
Aluminum oxide
Atomic layer deposited
Bottom gate
Dielectrics
Double gate
Double-Gate transistor
High quality
Integration approach
Logic gates
Process flows
Process steps
Shallow trench isolation
Silicon
Transistors
Ultra-thin
Wafer-scale processing
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Summary:In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for microelectronics integration: bottom gates with ultra-thin (2nm) high-quality thermally grown SiO 2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al 2 O 3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing and other graphene-based devices.
ISSN:1930-8876
DOI:10.1109/ESSDERC.2012.6343380