A Unified WCET analysis framework for multicore platforms

With the advent of multicore architectures, worst-case execution time (WCET) analysis has become an increasingly difficult problem. In this article, we propose a unified WCET analysis framework for multicore processors featuring both shared cache and shared bus. Compared to other previous works, our...

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Bibliographic Details
Published in:ACM transactions on embedded computing systems 2014-07, Vol.13 (4s), p.1-29
Main Authors: Chattopadhyay, Sudipta, Chong, Lee Kee, Roychoudhury, Abhik, Kelter, Timon, Marwedel, Peter, Falk, Heiko
Format: Article
Language:English
Subjects:
Architecture (computers)
Benchmarking
Buses (vehicles)
Embedded computer systems
Mathematical models
Microprocessors
Pipelines
Platforms
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Summary:With the advent of multicore architectures, worst-case execution time (WCET) analysis has become an increasingly difficult problem. In this article, we propose a unified WCET analysis framework for multicore processors featuring both shared cache and shared bus. Compared to other previous works, our work differs by modeling the interaction of shared cache and shared bus with other basic microarchitectural components (e.g., pipeline and branch predictor). In addition, our framework does not assume a timing anomaly free multicore architecture for computing the WCET. A detailed experiment methodology suggests that we can obtain reasonably tight WCET estimates in a wide range of benchmark programs.
ISSN:1539-9087
1558-3465
1558-3465
DOI:10.1145/2584654