Optimization of a bus-based test data transportation mechanism in system-on-chip

The increasing amount of test data needed to test SOC (system-on-chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the chip. Having a powerful TAM shorten the test time, but it costs large silicon area to implement it. Hence, it is importa...

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Bibliographic Details
Main Authors: Larsson, A., Larsson, E., Eles, P., Peng, Z.
Format: Conference Proceeding
Language:English
Subjects:
bus structure
Computer architecture
Computer science
Datavetenskap
Design optimization
Embedded system
Information technology
Informationsteknik
Packaging
Road transportation
Sequential analysis
Size control
System testing
System-on-a-chip
system-on-chip
TAM
TECHNOLOGY
TEKNIKVETENSKAP
test access mechanism
test data transportation
testing
Wires
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Summary:The increasing amount of test data needed to test SOC (system-on-chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the chip. Having a powerful TAM shorten the test time, but it costs large silicon area to implement it. Hence, it is important to have an efficient TAM with minimal required hardware overhead. We propose a technique that makes use of the existing bus structure with additional buffers inserted at each core to allow test application to the cores and test data transportation over the bus to be performed asynchronously. The non-synchronization of test data transportation and test application makes it possible to perform concurrent testing of cores while test data is transported in a sequence. We have implemented a Tabu search based technique to optimize our test architecture, and the experimental results indicate that it produces high quality results at low computational cost.
DOI:10.1109/DSD.2005.59