Microarchitecture of the Godson-2 Processor

The Godson project is the first attempt to design high performance general-purpose microprocessors in China. This paper introduces the microarchitecture of the Godson-2 processor which is a 64-bit, 4-issue, out-of-order execution RISC processor that implements the 64-bit MIPS-like instruction set. T...

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Bibliographic Details
Published in:Journal of computer science and technology 2005-03, Vol.20 (2), p.243-249
Main Authors: Hu, Wei-Wu, Zhang, Fu-Xin, Li, Zu-Song
Format: Article
Language:English
Subjects:
China
Computer networks
Corners
Dynamics
Loads (forces)
Macros
Micrometers
Microprocessors
RISC
RISC processors
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Summary:The Godson project is the first attempt to design high performance general-purpose microprocessors in China. This paper introduces the microarchitecture of the Godson-2 processor which is a 64-bit, 4-issue, out-of-order execution RISC processor that implements the 64-bit MIPS-like instruction set. The adoption of the aggressive out-of-order execution techniques (such as register mapping, branch prediction, and dynamic scheduling) and cache techniques (such as non-blocking cache, load speculation, dynamic memory disambiguation) helps the Godson-2 processor to achieve high performance even at not so high frequency. The Godson-2 processor has been physically implemented on a 6-metal 0.18μm CMOS technology based on the automatic placing and routing flow with the help of some crafted library cells and macros. The area of the chip is 6,700 micrometers by 6,200 micrometers and the clock cycle at typical corner is 2.3ns.
ISSN:1000-9000
1860-4749
DOI:10.1007/s11390-005-0243-6