Modular Timing Constraints for Delay-Insensitive Systems

This paper introduces ARCtimer, a framework for modeling, generating, verifying, and enforcing timing constraints for individual self-timed handshake components. The constraints guarantee that the component＇s gate-level circuit implementation obeys the component＇s handshake protocol specification. B...

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Bibliographic Details
Published in:Journal of computer science and technology 2016, Vol.31 (1), p.77-106
Main Authors: Park, Hoon, He, Anping, Roncken, Marly, Song, Xiaoyu, Sutherland, Ivan
Format: Article
Language:English
Subjects:
Analysis
Artificial Intelligence
Circuit design
Circuits
Communication channels
Computer engineering
Computer Science
Data Structures and Information Theory
Design
Design analysis
Design engineering
Handshaking protocols
Information Systems Applications (incl.Internet)
Integrated circuits
Libraries
Modular
Protocol
Protocol (computers)
Regular Paper
Science
Software Engineering
Static timing analysis
Studies
System built
Theory of Computation
Time measurements
Transistors
延迟
执行时间
握手协议
敏感系统
时序约束
时序验证
模块化
电路实现
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Summary:This paper introduces ARCtimer, a framework for modeling, generating, verifying, and enforcing timing constraints for individual self-timed handshake components. The constraints guarantee that the component＇s gate-level circuit implementation obeys the component＇s handshake protocol specification. Because the handshake protocols are delayinsensitive, self-timed systems built using ARCtimer-verified components are also delay-insensitive. By carefully considering time locally, we can ignore time globally. ARCtimer comes early in the design process as part of building a library of verified components for later system use. The library also stores static timing analysis （STA） code to validate and enforce the component＇s constraints in any self-timed system built using the library. The library descriptions of a handshake component＇s circuit, protocol, timing constraints, and STA code are robust to circuit modifications applied later in the design process by technology mapping or layout tools. In addition to presenting new work and discussing related work, this paper identifies critical choices and explains what modular timing verification entails and how it works.
ISSN:1000-9000
1860-4749
DOI:10.1007/s11390-016-1613-y