A Unified Buffering Management with Set Divisible Cache for PCM Main Memory

• Published in: Journal of computer science and technology 2016, Vol.31 (1), p.137-146
• Main Authors: Bian, Mei-Ying, Yoon, Su-Kyung, Kim, Jeong-Geun, Nam, Sangjae, Kim, Shin-Dug
• Format: Article
• Language: English
• Subjects: Adaptive structures; Analysis; Artificial Intelligence; Buffers; Computer memory; Computer Science; Data Structures and Information Theory; DRAM; Dynamic random access memory; Dynamical systems; Dynamics; Energy consumption; Information Systems Applications (incl.Internet); Management; Optimization; PCM; Regular Paper; Reuse; Software Engineering; Studies; Theory of Computation; 内存系统; 内存缓冲区; 动态随机存取存储器; 缓冲管理; 缓存设置; 自适应分块
• ISSN: 1000-9000; 1860-4749
• DOI: 10.1007/s11390-016-1617-7

This research proposes a phase-change memory （PCM） based main memory system with an effective combi- nation of a superblock-based adaptive buffering structure and its associated set divisible last-level cache （LLC）. To achieve high performance similar to that of dynamic random-access memory （DRAM） based main memory, the superblock-based adaptive buffer （SABU） is comprised of dual DRAM buffers, i.e., an aggressive superblock-based pre-fetching buffer （SBPB） and an adaptive sub-block reusing buffer （SBRB）, and a set divisible LLC based on a cache space optimization scheme. According to our experiment, the longer PCM access latency can typically be hidden using our proposed SABU, which can significantly reduce the number of writes over the PCM main memory by 26.44%. The SABU approach can reduce PCM access latency up to 0.43 times, compared with conventional DRAM main memory. Meanwhile, the average memory energy consumption can be reduced by 19.7%.