A Machine Learning Framework with Feature Selection for Floorplan Acceleration in IC Physical Design

• Published in: Journal of computer science and technology 2020-03, Vol.35 (2), p.468-474
• Main Authors: Zhang, Shu-Zheng, Zhao, Zhen-Yu, Feng, Chao-Chao, Wang, Lei
• Format: Article
• Language: English
• Subjects: Accuracy; Artificial Intelligence; Circuit design; Computer Science; Data Structures and Information Theory; Design; Discovery and exploration; Feature selection; Floorplans; Information Systems Applications (incl.Internet); Integrated circuits; Iterative methods; Machine learning; Memory (Computers); Model accuracy; Outer space; Rankings; Semiconductor chips; Short Paper; Software Engineering; Static random access memory; Theory of Computation
• ISSN: 1000-9000; 1860-4749
• DOI: 10.1007/s11390-020-9688-x

Floorplan is an important process whose quality determines the timing closure in integrated circuit (IC) physical design. And generating a floorplan with satisfying timing result is time-consuming because much time is spent on the generation-evaluation iteration. Applying machine learning to the floorplan stage is a potential method to accelerate the floorplan iteration. However, there exist two challenges which are selecting proper features and achieving a satisfying model accuracy. In this paper, we propose a machine learning framework for floorplan acceleration with feature selection and model stacking to cope with the challenges, targeting to reduce time and effort in integrated circuit physical design. Specifically, the proposed framework supports predicting post-route slack of static random-access memory (SRAM) in the early floorplan stage. Firstly, we introduce a feature selection method to rank and select important features. Considering both feature importance and model accuracy, we reduce the number of features from 27 to 15 (44% reduction), which can simplify the dataset and help educate novice designers. Then, we build a stacking model by combining different kinds of models to improve accuracy. In 28 nm technology, we achieve the mean absolute error of slacks less than 23.03 ps and effectively accelerate the floorplan process by reducing evaluation time from 8 hours to less than 60 seconds. Based on our proposed framework, we can do design space exploration for thousands of locations of SRAM instances in few seconds, much more quickly than the traditional approach. In practical application, we improve the slacks of SRAMs more than 75.5 ps (177% improvement) on average than the initial design.