A Self-Biased Low-Jitter Process-Insensitive Phase-Locked Loop for 1.25Gb/s-6.25Gb/s SerDes

• Published in: Chinese Journal of Electronics 2018-09, Vol.27 (5), p.1009-1014
• Main Authors: YUAN, Hengzhou, GUO, Yang, LIU, Yao, LIANG, Bin, GUO, Qiancheng
• Format: Article
• Language: English
• Subjects: accelerator; bit rate 1.25 Gbit/s to 6.25 Gbit/s; charge pump circuits; clocks; CMOS integrated circuits; damping factor; differential charge pump; frequency dividers; fully integrated multiphase output low‐jitter CMOS phase‐locked loop; high process insensitivity; jitter; jitter performance; low power supply; Low‐jitter; low‐power electronics; phase locked loops; Phase‐locked loop (PLL); process migration; Process‐insensitive; self‐adaptive frequency dividers; Self‐biased; self‐biased bandwidth technology; self‐biased low‐jitter process‐insensitive phase‐locked loop; Serializer‐deserializer; size 55.0 nm; size 65.0 nm; wireline SerDes transmitter clocking
• ISSN: 1022-4653; 2075-5597
• DOI: 10.1049/cje.2018.02.003

The paper presents a fully integrated multiphase output low-jitter CMOS phase-locked loop for 1.25Gb/s to 6.25Gb/s wireline SerDes transmitter clocking. The self-biased bandwidth technology with simplified structure is applied to reduce the sensitivity to process variations. A diffierential Charge pump (CP) which is suitable for low power supply and process migration is proposed. An accelerator is built to avoid the disadvantage of great damping factor. Self-adaptive frequency dividers are used to improve power efficiency. The simulation results under 65nm and 55nm process almost maintain almost the same jitter performance and show the high process insensitivity and good jitter performance.