Comparing techniques for spur reduction in digital bang-bang PLLs

Bang-bang phase-locked loops (PLLs) are prone to generate unwanted output spur tones and high noise floor. In this reported work, a spur reduction technique based on dithering is compared to an alternative technique which exploits oscillator intrinsic noise. It is shown how the latter, joined to a p...

Full description

Saved in:
Bibliographic Details
Published in:Electronics letters 2013-04, Vol.49 (8), p.527-529
Main Authors: Maffezzoni, P, Marucci, G, Levantino, S, Samori, C
Format: Article
Language:English
Subjects:
Applied sciences
Circuit properties
Circuits and systems
digital bang‐bang phase‐locked looper
digital bang‐bang PLL
digital phase locked loops
dithering
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
high noise floor
loop design
oscillator intrinsic noise
oscillators
Oscillators, resonators, synthetizers
spur reduction technique
unwanted output spur tones
Citations: Items that this one cites
Items that cite this one
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Bang-bang phase-locked loops (PLLs) are prone to generate unwanted output spur tones and high noise floor. In this reported work, a spur reduction technique based on dithering is compared to an alternative technique which exploits oscillator intrinsic noise. It is shown how the latter, joined to a proper loop design, allows eliminating unwanted spur tones while yielding a lower noise floor.
ISSN:0013-5194
1350-911X
1350-911X
DOI:10.1049/el.2012.4402