Energy aware simplicial processor for embedded morphological visual processing in intelligent internet of things

• Published in: Electronics letters 2018-04, Vol.54 (7), p.420-422
• Main Authors: Villemur, M, Julian, P, Andreou, A. G
• Format: Article
• Language: English
• Subjects: approximation theory; architecture implementation; CMOS digital integrated circuits; dynamic energy dissipation efficiency; dynamic voltage‐frequency scaling; eight‐neighbour clique; embedded morphological visual processing; energy aware simplicial processor; Image and vision processing and display technology; image processing; intelligent internet of things; Internet of Things; linear array; low‐power electronics; parallel processing; SIMD processor; simplicial piece‐wise linear approximation; size 55 nm; ultralow‐voltage CMOS library; voltage 0.6 V
• ISSN: 0013-5194; 1350-911X; 1350-911X
• DOI: 10.1049/el.2017.4738

This Letter presents the architecture implementation and testing of an single instruction multiple data (SIMD) processor for energy aware embedded morphological visual processing using the simplicial piece-wise linear approximation. The architecture comprises a linear array of 48 × 48 processing elements, each connected to an eight-neighbour clique operating on binary input and state data. The architecture is synthesised from a custom designed ultra low-voltage CMOS library and fabricated in a 55 nm CMOS technology. The chip is capable of dynamic voltage/frequency scaling with power supplies between 0.5 and 1.2 V. The fabricated chip achieves an overall performance of 293 TOPS/W with dynamic energy dissipation efficiency of 3.4 fJ per output operation at 0.6 V.