BBPD with wide input phase range

• Published in: Electronics letters 2019-03, Vol.55 (5), p.249-250
• Main Authors: Kossel, M, Francese, P, Morf, T, Brändli, M, Khatri, V, Yonar, S, Dazzi, M, Khaddam-Aljameh, R
• Format: Article
• Language: English
• Subjects: 2‐octave frequency range; bang‐bang phase detector; BBPD; Circuits and systems; clocks; CMOS digital integrated circuits; CMOS technology; control logic; differential clock; flip‐flops; frequency 4.0 GHz to 16.0 GHz; frequency dividers; fully symmetrical set‐reset latch; local frequency dividers; logic design; low‐power electronics; microwave detectors; MMIC; multiphase generator; multiphase signals; phase detectors; phase lagging; phase leading; power efficiency; pulse‐width extension circuitries; serialisers‐deserialisers; size 7.0 nm; wide input phase range; wireline communication circuits
• ISSN: 0013-5194; 1350-911X; 1350-911X
• DOI: 10.1049/el.2018.7755

Wireline communication circuits often include serialisers/deserialisers using multiphase signals for multiplexing or sampling. From a power efficiency viewpoint, configurations are desired in which a single differential clock at frequency f is distributed to decentralised multiphase generators as opposed to distribution at 2f with local frequency dividers. A bang–bang phase detector (BBPD) is presented for such a multiphase generator operated from 4 to 16 GHz. Owing to the 2-octave frequency range, a wide input phase range is required for which the BBPD may not generate false locks. This is achieved by an implementation in which down pulses at the output of a fully symmetrical set/reset latch are stretched via pulse-width extension circuitries. A sampling pulse generated from one of the input phases can then easily capture the extended down pulses across a wide input phase range to unambiguously indicate phase leading or phase lagging to the control logic of the multiphase generator. The proposed circuitry has been implemented in a 7 nm CMOS technology. A comparison to alternative BBPD approaches implemented in the same technology shows that the proposed architecture outperforms them in terms of achievable input phase range.