8.4-to-16-bit resolution, 1-to-16 kHz bandwidth ADC with programmable-gain functionality for multi-sensor applications

• Published in: Electronics letters 2019-09, Vol.55 (18), p.982-984
• Main Authors: Rhee, C, Kim, S
• Format: Article
• Language: English
• Subjects: analogue‐digital conversion; bio‐signals; Circuits and systems; CMOS integrated circuits; delta‐sigma modulation; low‐power electronics; modulators; multisensor system; PG first‐order NS successive‐approximation register analogue‐to‐digital converter; PG NS SAR ADC; programmable‐gain first‐order noise‐shaping SAR ADC; sensor fusion; third‐order delta‐sigma modulator; voltage 1.8 V
• ISSN: 0013-5194; 1350-911X; 1350-911X
• DOI: 10.1049/el.2019.1496

A resolution-reconfigurable, bandwidth-scalable analogue-to-digital converter (ADC) with programmable-gain (PG) functionality for a multi-sensor system, which encompasses various signals such as bio-signals and battery-level, is presented. In PG and low-power mode, a PG first-order noise-shaping (NS) successive-approximation register (SAR) ADC achieves 8.4-to-10.2-bit operating up to 16 kHz while providing a gain of 1/2/4. The PG NS SAR ADC can be reconfigured as an adder and a quantiser in a delta-sigma (ΔΣ) modulator enhancing the order of the modulator for high-resolution. The third-order ΔΣ modulator achieves 16.1 bits in a bandwidth of 1 kHz. The work is implemented in a 0.18 μm CMOS process with a 1.8 V power supply.