Architecture of a real-time delay calculator for digital beamforming in ultrasound system

• Published in: IET circuits, devices & systems devices & systems, 2016-07, Vol.10 (4), p.322-329
• Main Authors: Agarwal, Mayur, De, Arijit, Banerjee, Swapna
• Format: Article
• Language: English
• Subjects: 28-bit radicand hybrid square root calculator; 64-element convex transducer array; Accuracy; Algorithms; Approximation; approximation theory; Architecture (computers); array signal processing; Arrays; Beamforming; Calculators; Computer architecture; cyst image phantoms; Delay; digital beamforming; Digital imaging; Dynamic focusing; Dynamical systems; Dynamics; Field II toolbox; Hardware; hardware architecture; hardware consumption; Image quality; Iterative methods; linear approximation; Mathematical analysis; Matlab; Methods; multielement transducer array; on-line computation; phased array imaging; Phased arrays; quadratic approximation; real-time delay calculator; scan lines; scan points; Signal quality; synthetic transmit aperture; Time lag; Transducers; Ultrasonic imaging; ultrasound system
• ISSN: 1751-858X; 1751-8598; 1751-8598
• DOI: 10.1049/iet-cds.2015.0189

In ultrasound systems synthetic transmit aperture and phased array imaging are widely used for obtaining the high quality images. These imaging systems require dynamic focusing of the multi-element transducer array at large number of scan points during transmission and reception. The array can be focused at any point by applying proper delay values to the signals, received or transmitted by each element of the array. Dynamic focusing requires on-line computation of the delay values, for large number of scan points, corresponding to all the elements of the array. This paper describes a delay calculation algorithm and corresponding hardware architecture for dynamically focusing the convex transducer array at large number of scan points. The hardware architecture for the 64-element convex transducer array, which scans 128 scan lines having 1024 scan points on each scan line, consumes 61k gates. It shows around 57–86% improvement in terms of hardware consumption with respect to those of other available architectures. To reduce the overall complexity and latency of the delay calculator, a 28- bit radicand square root calculator architecture which requires less initial memory than that of the linear approximation and less hardware resources than that of the quadratic approximation is also presented.