Design optimisation procedure for digital mismatch compensation in latch comparators

• Published in: IET circuits, devices & systems devices & systems, 2018-11, Vol.12 (6), p.726-734
• Main Authors: Khanfir, Leïla, Mouïne, Jaouhar
• Format: Article
• Language: English
• Subjects: Algorithms; Calibration; calibration accuracy; calibration control; calibration resolution; circuit optimisation; CMOS; CMOS logic circuits; comparator performance; Comparators; comparators (circuits); compensation; complementary metal–oxide–semiconductor technology; Configuration management; design optimisation procedure; Design optimization; Design parameters; digital calibration schemes; digital mismatch compensation; dynamic comparators; flip-flops; high-speed operation; integrated circuit design; latch comparator; logic design; low-power electronics; post-layout statistical simulations; Random access memory; reduced power consumption; simple digital sequencer; size 0.18 mum; Special Issue: Low Voltage Low Power Integrated Circuits and Systems; three-step design procedure; Transistors; word length 5.9 bit; word length 7.0 bit
• ISSN: 1751-858X; 1751-8598; 1751-8598
• DOI: 10.1049/iet-cds.2018.5153

Digital calibration schemes generally allow for high-speed operation and reduced power consumption at the price of lower accuracy compared with their analogue counterparts. However, in dynamic comparators, when exceeding 4 or 5 bits, any resolution increase will be progressively traded against the circuit parameters. This study presents a three-step design procedure to optimise the comparator performance for a given N. First, a new configuration of the latch comparator has allowed optimising the comparison speed in terms of N. Second, the calibration scheme has been reduced to a simple digital sequencer to perform a progressive capacitive offset trimming. Third, the sequencer automatic increment has been programmed to stop at optimal operation to achieve the best calibration accuracy. The proposed method has then been applied to design a latch comparator with 7 bit calibration control in a commercially available 0.18 µm complementary metal–oxide–semiconductor technology. Post-layout statistical simulations have shown that the circuit can achieve up to 5.9 bit calibration resolution without altering the comparator performances.