Energy-efficient fault tolerant technique for deflection routers in two-dimensional mesh Network-on-Chips

• Published in: Chronic diseases and translational medicine 2018-05, Vol.12 (3), p.69-79
• Main Authors: Sleeba, Simi Zerine, Jose, John, Mini, Maniyelil Govindankutty
• Format: Article
• Language: English
• Subjects: Algorithms; buffer‐less routers; chip reliability; Communication; deep submicron level feature sizes; deflection router pipeline; dynamic power consumption reduction; Energy efficiency; energy‐efficient fault‐tolerant technique; Fault tolerance; fault tolerant computing; flit deflection rate; high fault rates; hop power; integrated circuit reliability; inter‐router links; logic unit; network routing; network‐on‐chip; new generation multiprocessor system‐on‐chips; NoC links; on‐chip communication networks; output port allocation stage; permanent faults; Research Article; SoC; two‐dimensional mesh network‐on‐chips
• ISSN: 1751-8601; 1751-861X; 2095-882X; 1751-861X; 2589-0514
• DOI: 10.1049/iet-cdt.2017.0006

New generation multi-processor system-on-chips integrate hundreds of processing elements in a single chip which communicate with each other through on-chip communication networks, commonly known as network-on-chip (NoC). Routers are the most critical NoC components and deflection routing is a technique used in buffer-less routers for better energy efficiency. Massive integration of devices along with fabrication at deep sub-micron level feature sizes increases the possibility of wear out and damage to various components resulting in unreliable operation of the chip. Hence NoC fabric in general and routers, in particular, should be equipped with built-in fault tolerance mechanisms to ensure the reliability of the chip in the presence of faults. The authors propose an energy-efficient routing technique that can tolerate permanent faults in NoC links by introducing a simple logic unit placed next to the output port allocation stage of the deflection router pipeline. This technique incurs minimum wiring overheads and promises a stable network throughput for high fault rates. Evaluation of the proposed method on 8 × 8 mesh NoC for various fault rates reports reduced flit deflection rate and hop power which brings about a significant reduction in dynamic power consumption at the inter-router links compared to state-of-the-art fault tolerance techniques.