Loading…
Compressed instruction cache architecture for high-performance embedded RISC systems
The influence of embedded systems is felt in many aspects of our daily lives; being particularly apparent in consumer electronics and automotive products. Customer demand and rapid advances in the complexity of the underlying technology has enabled the introduction of new systems and services that w...
Saved in:
| Main Author: | |
|---|---|
| Format: | Default Thesis |
| Published: |
2007
|
| Subjects: | |
| Online Access: | https://hdl.handle.net/2134/33689 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Summary: | The influence of embedded systems is felt in many aspects of our daily lives; being particularly apparent in consumer electronics and automotive products. Customer demand and rapid advances in the complexity of the underlying technology has enabled the introduction of new systems and services that were simply not feasible just a few years ago. Although the cost of embedded systems is an important design parameter, their development is also affected by performance and functionality. The performance issue is traditionally addressed by the design of faster microprocessors, but more recently by the exploitation of parallelism (for example, vector units and very long instruction word processors), as well as special purpose hardware architectures, such as graphics processing units and network cards. In such systems, however, the main performance bottleneck is often the memory hierarchy, particularly in systems with complex memory access arbitration, where read or write operations to the main memory could result in delays of thousands of cycles. AI though the widespread use of cache memories aims to alleviate this effect to some extent, memory access penalties remain a significant drain on performance. Functionality is closely related to the memory capacity available, particularly in portable systems such as mobile phones and handheld games consoles. The work described in this thesis includes a comprehensive analysis of code size and performance issues of embedded reduced instruction set computer architectures. [Continues.] |
|---|