Parametric data-parallel architectures for TLM acceleration

We discuss the architecture and microarchitecture of a scalable, parametric vector accelerator for the TLM algorithm. Architecture-level experimentation demonstrates an order of magnitude complexity reduction for vector lengths of 16 32-bit single-precision elements. We envisage the proposed archite...

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Bibliographic Details

Main Authors:	Vassilios Chouliaras, James Flint, Yibin Li
Format:	Default Conference proceeding
Published:	2004
Subjects:	Mechanical engineering not elsewhere classified untagged Mechanical Engineering not elsewhere classified
Online Access:	https://hdl.handle.net/2134/6168
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