Gate-Tunable Negative Differential Resistance in WSe2/h-BN/Graphene Heterostructure

• Published in: ACS applied nano materials 2025-01, Vol.8 (1), p.535-542
• Main Authors: Uddin, Inayat, Phan, Nhat Anh Nguyen, Le Thi, Hai Yen, Yoo, Won Jong, Watanabe, Kenji, Taniguchi, Takashi, Khan, Muhammad Atif, Kim, Gil-Ho
• Format: Article
• Language: English
• ISSN: 2574-0970; 2574-0970
• DOI: 10.1021/acsanm.4c05907

Negative differential resistance (NDR) devices show potential for advanced future computing technologies with deficient energy consumption, particularly in multivalued logic computing due to multiple threshold voltages. Here, we report an NDR phenomenon observed in a heterostructure of graphene (Gr), hexagonal boron nitride (h-BN), and tungsten diselenide (WSe2) in the negative gate voltage regime. In this structure, WSe2 is employed as a channel material aligned with a dielectric, h-BN, while Gr acts as a floating gate. The investigation of temperature-dependent electrical charge transport using the global gate allows for identifying the tunneling process within a specific range of gate voltages. In addition, the electrical charge transport measurement demonstrates significant gate-tunable NDR behavior with a maximum peak-to-valley current ratio of 7.2 at room temperature, which improved to 11.6 at a temperature of 77 K. To the best of our knowledge, this is the unique demonstration of NDR charge transport behavior in a single-channel WSe2 field-effect transistor device. This feature promises many applications, such as low-power logical circuits, memory, and high-frequency switching devices.