System-level design based on UML/MARTE for FPGA-based embedded real-time systems

• Published in: Design automation for embedded systems 2016-06, Vol.20 (2), p.127-153
• Main Authors: Leite, Marcela, Wehrmeister, Marco Aurélio
• Format: Article
• Language: English
• Subjects: CAE) and Design; Circuits and Systems; Computer-Aided Engineering (CAD; Engineering; Special Purpose and Application-Based Systems
• ISSN: 0929-5585; 1572-8080
• DOI: 10.1007/s10617-016-9172-6

This paper discusses an approach to generate VHDL descriptions from high-level specifications, namely UML/MARTE models that include aspect-oriented semantics. Standard UML diagrams describe the handling of functional requirements, whereas crosscutting concerns associated with the non-functional requirements are handled by aspects. UML-to-VHDL transformation is performed automatically by a script-based code generation tool named GenERTiCA. For that, mapping rules scripts define how to generate VHDL constructs from model elements, including the implementation of aspects adaptations. The generated VHDL description does not require any manual modification, in order to be fully synthesized onto a FPGA device. Some case studies have been performed to evaluate the proposed approach, including examples of real systems implemented as a FPGA-based embedded system. Obtained results show an improvement in system design in terms of an increase in system performance as well as a better utilization of FPGA reconfigurable resources. Such positive results are related to a better modularization of components achieved by using the proposed high-level approach. These case studies demonstrate the practicability of full translation of platform-independent specifications into VHDL descriptions.