A loss aware scalable topology for photonic on chip interconnection networks

• Published in: The Journal of supercomputing 2014-04, Vol.68 (1), p.106-135
• Main Authors: Reza, Akram, Sarbazi-Azad, Hamid, Khademzadeh, Ahmad, Shabani, Hesam, Niazmand, Behrad
• Format: Article
• Language: English
• Subjects: Compilers; Computer Science; Interpreters; Processor Architectures; Programming Languages
• ISSN: 0920-8542; 1573-0484
• DOI: 10.1007/s11227-013-1026-4

The demand for robust computation systems has led to the increment of the number of processing cores in current chips. As the number of processing cores increases, current electrical communication means can introduce serious challenges in system performance due to the restrictions in power consumption and communication bandwidth. Contemporary progresses in silicon nano-photonic technology have provided a suitable platform for constructing photonic communication links as an alternative for overcoming such problems. Topology is one of the most significant characteristics of photonic interconnection networks. In this paper, we have introduced a novel topology, aiming to reduce insertion loss in photonic networks; detailed analysis of the proposed topology has also been provided based on synthetic and real application benchmarks using a cycle-accurate simulation environment. Results demonstrate that the proposed topology outperforms other considered topologies in terms of physical-layer parameters, such as insertion loss, and provides better scalability. Moreover, such improvement in physical-layer parameters has caused system performance parameters to improve significantly. For instance, the topology yields an improvement of at least 406 % in bandwidth, compared to the best case, when leveraging synthetic traffic patterns. Furthermore, when using scientific applications, execution time and energy efficiency are improved up to 85 % and 97 %, respectively.