Hardware design of the multris microprocessor

The MULTRIS ( MULTitasking RISC) is a RISC-type processor, developed at George Mason University and is targeted for multitasking languages. It implements an efficient register management policy called Threaded Register Windows, described in [10]. Each task running on MULTRIS can directly access six...

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Bibliographic Details
Published in:Microprocessing and microprogramming 1990-03, Vol.28 (1), p.117-122
Main Authors: Leeuwrik, G., Miller, D.R., Quammen, D., Senko, R., Tabak, D.
Format: Article
Language:English
Subjects:
Applied sciences
Computers, microcomputers
Electronics
Exact sciences and technology
Hardware
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Summary:The MULTRIS ( MULTitasking RISC) is a RISC-type processor, developed at George Mason University and is targeted for multitasking languages. It implements an efficient register management policy called Threaded Register Windows, described in [10]. Each task running on MULTRIS can directly access six windows at a time. Window assignments can be varied by instructions such as a procedure call, etc. There are currently 64 non-overlapping windows. When a task switch occurs, the new task acquires other windows in the CPU, while the interrupted task keeps its own windows. As long as there are free windows in the CPU, no CPU-memory traffic occurs during a task switch. This policy yields a very efficient multitasking system, particularly useful in supporting real-time applications and tasking languages. The purpose of this paper is to report the second stage of the MULTRIS development, namely its architectural and hardware design. The distinguishing features of this architecture include multiple register resident stacks, and queues; burst mode register-memory transfer; and low latency interrupt support.
ISSN:0165-6074
DOI:10.1016/0165-6074(90)90159-7