Tensor slicing and optimization for multicore NPUs

• Published in: Journal of parallel and distributed computing 2023-05, Vol.175, p.66-79
• Main Authors: Sousa, Rafael, Pereira, Marcio, Kwon, Yongin, Kim, Taeho, Jung, Namsoon, Kim, Chang Soo, Frank, Michael, Araujo, Guido
• Format: Article
• Language: English
• Subjects: Burst-based cost model; Convolutional neural network; Mapping strategies; NPU
• ISSN: 0743-7315; 1096-0848
• DOI: 10.1016/j.jpdc.2022.12.008

Although code generation for Convolution Neural Network (CNN) models has been extensively studied, performing efficient data slicing and parallelization for highly-constrained Multicore Neural Processor Units (NPUs) is still a challenging problem. Given the size of convolutions' input/output tensors and the small footprint of NPU on-chip memories, minimizing memory transactions while maximizing parallelism and MAC utilization are central to any effective solution. This paper proposes a TensorFlow XLA/LLVM compiler optimization pass for Multicore NPUs, called Tensor Slicing Optimization (TSO), which: (a) maximizes convolution parallelism and memory usage across NPU cores; and (b) reduces data transfers between host and NPU on-chip memories by using DRAM memory burst time estimates to guide tensor slicing. To evaluate the proposed approach, a set of experiments was performed using the NeuroMorphic Processor (NMP), a multicore NPU containing 32 RISC-V cores extended with novel CNN instructions. Experimental results show that TSO is capable of identifying the best tensor slicing that minimizes execution time for a set of CNN models. Speed-ups of up to 21.7% result when comparing the TSO burst-based technique to a no-burst data slicing approach. To validate the generality of the TSO approach, the algorithm was also ported to the Glow Machine Learning framework. The performance of the models were measured on both Glow and TensorFlow XLA/LLVM compilers, revealing similar results. •A burst-based cost model for Tensor Slicing Optimization.•Reducing data transfer between host and NPU on-chip memories.•Maximizing Convolution parallelism and memory reuse.